Elevated source/drain junction metal oxide semiconductor field effect transistors (MOSFETs) have been proposed to eliminate the short channel and drain-induced barrier lowering (DIBL) effects of scaled submicron transistors. Fabrication of the elevated source/drain junction structure using conventional prior art methods requires the use of selective epitaxial semiconductor growth or selective silicon growth (SSG). For example, see Rodder, et al., U.S. Pat. No. 5,198,378, issued Mar. 30, 1993 and assigned to the assignee of this application. The elevated source/drain Junction structure allows formation of source/drain junctions with very shallow electrical junction depth from the surface of the MOSFET channel, along with low sheet resistance, self-aligned silicide layers on the surfaces of the elevated source/drain junctions. Device structures with elevated source/drain junctions allow formation of relatively thick, self-aligned silicide layers without the problem of excessive junction leakage.
The elevated source/drain junction structures are expected to be useful for transistors having line width or channel length dimensions (i.e., transistors having a gate length from source to drain) of 0.25.mu. or less. However, successful implementation of elevated source/drain junction structures requires reliable selective epitaxial silicon growth or selective polycrystalline or amorphous silicon growth processes and related fabrication equipment. However, these processes and related equipment have many problems related to process performance, deposition selectivity controls, facet formation, and process contamination sensitivity problems. Also, most selective silicon growth (SSG) processes are optimally performed at temperatures greater than 700.degree. C., which may cause transistor reliability degradations due to presence of hydrogen in the silicon deposition process medium. Moreover, higher deposition temperatures (T.gtoreq.850.degree. C.) typically used for the SEG process can result in redistribution of the dopant profiles in the IGFET device structure such as the channel dopant profile and the source/drain lightly doped drain (LDD). These problems indicate that there is a need for a fabrication method for forming elevated source/drain junction structures without the use of selective epitaxial semiconductor growth or selective semiconductor growth processes.